The present invention relates to the field of semiconductor processing, and, more particularly, to a method and apparatus for increasing the yield of semiconductor wafers.
Semiconductor wafer processing typically involves a sequence of process steps to form dies on the surface of a silicon wafer. At the completion of the process steps, a plurality of tests are performed on each die to determine good dies and failed dies. Up to several hundred individual tests may be performed on each die. Because of semiconductor wafer processing variations and undetected defects, the wafer may have passed all the in-process checks yet still have many dies that do not function.
After the dies have been tested, they are separated from the wafer by sawing or scribe-and-break techniques. The good dies identified at wafer sort are typically put in a protective or encapsulated package. After the good dies have been packaged, the plurality of tests are performed on the good dies after packaging to determine good packaged dies and failed packaged dies. These tests are typically performed at an increased temperature, which results in some of the good dies becoming failed packaged dies. Even though the wafer yield at package level is very high, there is still a need to improve the yield.
This problem is often compounded when the dies includes analog circuits because the collected test data will vary over a range. In contrast, collected test data for digital circuits are either a logic level 0 or a logic level 1. There is no variance. If collected test data for the analog circuits is on the edge of its desired range, i.e., a large variance, this is an indication that the same test performed at package level may likely cause the data to drift outside the desired range, thus causing the packaged die to fail.
There are typically three different groups involved in wafer yield analysis. A first group is the wafer level group located where the wafers are formed, a second group in the package level group located where the dies are packaged, and a third group is the product engineering core group which may not be collocated with the wafer level and package level groups. Each of these groups uses a different approach in their analysis for increasing wafer yield.
The wafer level group use software bin categories, good chips per wafer (GCW) and good to functional (GTF) numbers to control the yield. A first alarm is generated when GCW decreases. A subsequent step is to look at the GTF, and then to the bin categories. Once the impacting category is detected, the procedure transitions from looking for patterns in the wafer maps to correlation analysis with electrical test data or the process steps.
There are at least two negative implications using these numbers. The programs have at least 300 tests, and the number of software bin categories is very limited. Typically, there are about 25 bins. Consequently, one bin category represents several different tests. Sometimes two different problems are impacting in the same bin, which implies too much noise on the analysis.
A second problem is related to the use of the number of chips per wafer. A minimum group of failing wafer lots is needed to run correlation analysis, which means an extra waiting time. Another factor in the wafer fab environment is cycle time. Wafers are tested and immediately sent to the packaging factory. Recovery of failing dies is almost impossible.
The wafer level group is also interested in the package results of their devices. Test data at the package level is very different, even in the binning. Instead of software bins, the package level group uses hardware bins, which do not match with the software bins. This mismatch in storing the collected data reduces the analysis capability.
The package level group use a different approach to wafer yield analysis. The working material is the packaged devices themselves. Failed packaged devices can be stored and re-tested, for example, after a test program issue has been solved. Moreover, the testing environment is more flexible. Package level test databases are loaded with hardware bin data. These bins represent four different categories: good devices, functional, parametric and contact failures.
These categories define about 8 bins at the package level as compared to the 25 bins at the wafer level. Consequently, the 300 tests performed at the wafer level are now divided into a more limited number of bins. At least one of the 300 tests is generally responsible for a failed packaged die since the impact of a packaging process error on yield is rare. A packaging process error typically shows up as a contact or functional failure, which is relatively straightforward to identify.
The wafer level and package level groups have to deal with many different devices and technologies. Due to this fact, they cannot know each product in detail. Their analysis tools tend to be generic, and applicable to all products.
The product engineering core group includes engineers with a detailed knowledge of the devices. Studies done by this group explore the particularities of each device. Consequently, each test is analyzed separately. The product engineering core group uses a system of prioritization, which identifies the most yield impacting tests so that their efforts can be focused on the tests at the top of the list. Special data analysis tools are used as well as special routines developed by the product engineering core group.
Notwithstanding the above described efforts of the wafer level group, the package level group, and the product engineering core group, there is still a need to improve wafer yield after good dies have been packaged.
In view of the foregoing background, it is therefore an object of the present invention to efficiently determine yield impacting tests at wafer level and package level for increasing wafer yield.
It is yet another object of the present invention to define a database of the yield impacting tests so that the information may be accessed by other semiconductor manufacturing facilities for world-wide monitoring.
These and other objects, features and advantages in accordance with the present invention are provided by a method for processing semiconductor wafers, which includes forming a plurality of wafers each comprising a plurality of dies, performing a plurality of tests on the plurality of dies to determine good dies and failed dies, and packaging the good dies. The plurality of tests are preferably performed on the good dies after packaging to determine good packaged dies and failed packaged dies. A determination is preferably made as to which tests indicate both failed dies and failed packaged dies so that corrective action may be implemented. The method according to the present invention thus determines the yield impacting tests at wafer level and package level for increasing wafer yield.
Each die preferably includes analog circuits. Each performing of the plurality of tests preferably comprises applying analog input signals to each die, and measuring analog output signals therefrom. The method according to the present invention is particularly advantageous to dies including analog circuits since the test data values vary over a broader range, as compared to digital circuits having only a pass/fail criteria. Consequently, the test data can be analyzed so that a more thorough analysis may be provided.
The method preferably further includes prioritizing the plurality of tests performed on the dies based upon the failed dies, and prioritizing the plurality of tests performed on the packaged good dies based upon the failed packaged dies. The method preferably further includes defining a database based upon the prioritized tests performed on the dies and based upon the prioritized tests performed on the good dies after packaging. The database preferably comprises data collected at different manufacturing facilities. The database may be preferably accessed via the Internet so that so that other facilities processing the same type devices can review and compare the information to their own data. In other words, a global or worldwide monitoring of the test data is made available. It is thus possible to determine if a possible change on the test limits for a particular semiconductor wafer processing facility will effect the performance of the same test in another facility.
The method preferably further comprises calculating statistical data based upon the plurality of tests performed on the dies, and calculating statistical data based upon the plurality of tests performed on the good dies after packaging. The method preferably further comprises graphically displaying the statistical data for the tests. The statistical data preferably comprises mean and standard deviations for the tests.
Another aspect of the present invention is an apparatus comprising a first tester for performing a plurality of tests on a plurality of wafers each comprising a plurality of dies to determine good dies and failed dies, and a second tester for performing the plurality of tests on the good dies after packaging to determine good packaged dies and failed packaged dies. A processor is preferably connected to the first tester and to the second tester for determining which tests indicate both failed dies and failed packaged dies so that corrective action may be taken.
Each die preferably comprises analog circuits. The first and second testers each preferably perform the plurality of tests by applying analog input signals to each die, and measuring analog output signals therefrom. The processor preferably prioritizes the plurality of tests performed on the dies based upon the failed dies, and prioritizes the plurality of tests performed on the packaged good dies based upon the failed packaged dies.
A memory is preferably connected to the processor. The memory preferably stores a database based upon the prioritized tests performed on the dies and based upon the prioritized tests performed on the good dies after packaging. The database is preferably accessible via the Internet so that so that other facilities processing the same type devices can review and compare the information to their own data.
The processor preferably calculates statistical data based upon the plurality of tests performed on the dies, and calculates statistical data based upon the plurality of tests performed on the good dies after packaging. The apparatus preferably further includes a display connected to the processor for graphically displaying the statistical data for the tests.